UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 958

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

956
2nd edition
Edition
Change of Figure 13-99. Flowchart of Stop Condition Generation
Addition of setting and Note to Table 13-4. Operating Clock Selection
Addition of 13.9 Relationship Between Register Settings and Pins
Change of Figure 16-9. Example of Setting for UART Consecutive Reception +
ACK Transmission
Additions of description to 16.6 (4) DMA pending instruction
Change of Table 17-1. Interrupt Source List
Change of A/D converter and serial interface (IIC0) in Table 19-1. Operating
Statuses in HALT Mode (2/2)
Additions of Note to Figure 19-3. HALT Mode Release by Reset by Interrupt
Request Generation
Change of Figure 19-4. HALT Mode Release by Reset
Additions of Notes 2 to Figure 19-5. Operation Timing When STOP Mode Is
Released
Addition of Note to Figure 19-6. STOP Mode Release by Interrupt Request
Generation
Change of reset processing in Figure 19-7. STOP Mode Release by Reset
Change of description in (4)
Change of Figure 20-2. Timing of Reset by RESET Input
Change of Figure 20-4. Timing of Reset in STOP Mode by RESET Input
Change of Caution 2 in Figure 20-5. Format of Reset Control Flag Register
(RESF)
Change of Figure 21-2. Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (1/2)
Change of Figure 21-2. Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (2/2) and addition of Notes 5
Change of Figure 21-3. Example of Software Processing After Reset Release
Change of Note 4 in Figure 22-2. Format of Low-Voltage Detection Register
(LVIM) and addition of Cautions 3
Change of Cautions 2 in Figure 22-3. Format of Low-Voltage Detection Level
Select Register (LVIS)
Change of <5> in 22.4.1 (1) (a)
Change of Notes 2 in Figure 22-5. Timing of Low-Voltage Detector Internal Reset
Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Change of description and Caution in 22.4.1 (1) (b)
Change of Figure 22-6. Timing of Low-Voltage Detector Internal Reset Signal
Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 0) and Note
Change of <4> in 22.4.1 (2)
Change of Notes 2 in Figure 22-7. Timing of Low-Voltage Detector Internal Reset
Signal Generation (Bit: LVISEL = 1)
Change of <5> in 22.4.2 (1)
Additions of Notes 3 to Figure 22-8. Timing of Low-Voltage Detector Interrupt
Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
APPENDIX C REVISION HISTORY
User’s Manual U18432EJ5V0UD
Description
CHAPTER 13 SERIAL
ARRAY UNIT
CHAPTER 16 DMA
CONTROLLER
CHAPTER 17
INTERRUPT
FUNCTIONS
CHAPTER 19
STANDBY FUNCTION
CHAPTER 20 RESET
FUNCTION
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Chapter
(4/13)