UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 924

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

922
Timer
array unit
Operation of
timer array
unit as
independent
channel
Operation
of plural
channels of
timer array
unit
Function
Channel output
(TOmn pin)
operation
Collective
manipulation of
TOmn bits
Input pulse
interval
measurement
Input signal
high-/low-level
width
measurement
PWM function
Details of
Function
When TOEmn = 1, even if the output by timer interrupt of each timer (INTTMmn)
contends with writing to TOmn, output is normally done to TOmn pin.
(2) Default level of TOmn pin and output level after timer operation start
The following figure shows the TOmn pin output level transition when writing has
been done in the state of TOEmn = 0 before port output is enabled and TOEmn = 1
is set after changing the default level.
(a) When operation starts with TOMmn = 0 setting (toggle output)
(b) When operation starts with TOMmn = 1 setting (combination operation mode
(3) Operation of TOmn pin in combination operation mode (TOMmn = 1)
(a) When TOLmn setting has been changed during timer operation
(b) Set/reset timing
The TImn pin input is sampled using the operating clock selected with the CKSmn bit
of the TMRmn register, so an error equal to the number of operating clocks occurs.
The TImn pin input is sampled using the operating clock selected with the CKSmn bit
of the TMRmn register, so an error equal to the number of operating clocks occurs.
To rewrite both TDRmn of the master channel and TDRmp of the slave channel, a
write access is necessary two times. The timing at which the values of TDRmn and
TDRmp are loaded to TCRmn and TRCmp is upon occurrence of INTTMmn of the
master channel. Thus, when rewriting is performed split before and after occurrence
of INTTMmn of the master channel, the TOmp pin cannot output the expected
waveform. To rewrite both TDRmn of the master and TDRmp of the slave, therefore,
be sure to rewrite both the registers immediately after INTTMmn is generated from
the master channel.
The setting of TOLmn is invalid when TOMmn = 0. When the timer operation
starts after setting the default level, the toggle signal is generated and the output
level of TOmn pin is reversed.
(PWM output))
When TOMmn = 1, the active level is determined by TOLmn setting.
When the TOLmn setting has been changed during timer operation, the setting
becomes valid at the generation timing of TOmn change condition. Rewriting
TOLmn does not change the output level of TOmn. The following figure shows
the operation when the value of TOLmn has been changed during timer operation
(TOMmn = 1).
To realize 0%/100% output at PWM output, the TOmn pin/TOmn set timing at
master channel timer interrupt (INTTMmn) generation is delayed by 1 count clock
by the slave channel.
If the set condition and reset condition are generated at the same time, a higher
priority is given to the latter.
Figure 7-31 shows the set/reset operating statuses where the master/slave
channels are set as follows.
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
Cautions
pp.278,
279
pp.279,
280
p.282
p.301
p.305
p.309
(10/35)
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