UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 306

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
304
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAU stop
Figure 7-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7),
mn = 00 to 07, 10 to 13
Sets the TAU0EN bit, TAU1EN bit of the PER0 register to 1.
Sets the TPSm register.
Sets the TMRmn register (determines operation mode of
channel).
Sets TSmn bit to 1.
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
The TDRmn register can always be read.
The TCRmn register can always be read.
The TSRmn register can always be read.
Set values of the TOMmn, TOLmn, TOmn, and TOEmn
bits cannot be changed.
The TTmn bit is set to 1.
The TAU0EN bit, TAU1EN bit of the PER0 register is
cleared to 0.
Determines clock frequencies of CKm0 and CKm1.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEmn = 1, and count operation starts.
Counter (TCRmn) counts up from 0000H. When the TImn
pin input valid edge is detected, the count value is
transferred (captured) to TDRmn. At the same time,
TCRmn is cleared to 0000H, and the INTTMmn signal is
generated.
If an overflow occurs at this time, the OVF bit of the
TSRmn register is set; if an overflow does not occur, the
OVF bit is cleared.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
TCRmn is cleared to 0000H at the count clock input.
When the MDmn0 bit of the TMRmn register is 1,
INTTMmn is generated.
TCRmn holds count value and stops.
The OVF bit of the TSRmn register is also held.
All circuits are initialized and SFR of each channel is
also initialized.
Hardware Status