UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 691

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UPD78F1174AGF-GAT-AX

Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1174AGF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Remarks 1. f
Item
System clock
CPU
Flash memory
RAM
Port (latch)
External bus interface
Timer array unit (TAU)
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Serial array unit (SAU)
Serial interface (IIC0)
Multiplier
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Main system clock
Subsystem clock
f
IL
2. A
STOP Mode Setting
f
f
f
f
D
AD
IH
X
EX
XT
IL
XX
:
XX
:
:
:
:
XX
:
:
: Multiplexed address/data bus
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
Internal low-speed oscillation clock
Address bus
Data bus
f
f
f
f
IH
X
EX
XT
Clock supply to the CPU is stopped
Stopped
Status before STOP mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
Operation stopped
Operation stopped
Operation stopped. However, status before STOP mode was set is retained at voltage higher
than POC detection voltage.
Status before STOP mode was set is retained
Operation stopped. Status of each pin
Operation stopped
Operable
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Operable only when subsystem clock is selected as the count clock
Operation stopped
Operation stopped (the pin in Hi-Z status)
Operation stopped
Operable
When CPU Is Operating on
Table 19-2. Operating Statuses in STOP Mode
Oscillation Clock (f
Internal High-Speed
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
CHAPTER 19 STANDBY FUNCTION
User’s Manual U18432EJ5V0UD
IH
)
When CPU Is Operating on
CKOUT: Low level
AD15 to AD0 or D15 to D0: High impedance
A19 to A0: Retains status before STOP mode was set
RD, WR0, WR1: High level
ASTB: Low level
WAIT: High impedance
X1 Clock (f
X
)
External Main System Clock
When CPU Is Operating on
(f
EX
)
689

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