UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 235

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Example of setting procedure when using the subsystem clock as the CPU clock
(3) Example of setting procedure when stopping the subsystem clock
<1> Setting subsystem clock oscillation
<2> Setting the subsystem clock as the source clock of the CPU clock (CKC register)
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to
<1> Confirming the CPU clock status (CKC register)
<2> Stopping the subsystem clock (CSC register)
Cautions 1. Be sure to confirm that CLS = 0 when setting XTSTOP to 1.
(See 6.6.3 (1) Example of setting procedure when oscillating the subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock (See Figure 6-15 CPU Clock Status Transition
Diagram or Table 6-5 Changing CPU Clock for the conditions to change the subsystem clock to
another clock).
When XTSTOP is set to 1, subsystem clock is stopped.
CSS
CLS
the peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer).
guaranteed.
chapters describing the various peripheral hardware as well as CHAPTER 29 ELECTRICAL
SPECIFICATIONS
SPECIFICATIONS ((A) GRADE PRODUCTS).
0
0
1
1
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
peripheral hardware if it is operating on the subsystem clock.
f
SUB
MCS
/2
0
1
×
For the operating characteristics of the peripheral hardware, refer to the
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
At this time, the operations of the A/D converter and IIC0 are not
(STANDARD
CHAPTER 6 CLOCK GENERATOR
Selection of CPU/Peripheral Hardware Clock (f
User’s Manual U18432EJ5V0UD
Note
PRODUCTS)
CPU Clock Status
and
CHAPTER
CLK
)
30
In addition, stop the
ELECTRICAL
233