UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 931

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A/D
converter
D/A
converter
Function
A/D conversion
result register
(ADCR,
ADCRH) read
operation
Internal
equivalent circuit
Starting the A/D
converter
PER0:
Peripheral
enable register 0
Operation in
normal mode
Operation in
real-time output
mode
I/O function of
digital ports
alternately used
as ANO0, ANO1
P11, PM11
registers
ANO0, ANO1
pins
DACSn register
Changing
operation mode
Port alternately
used as ANO0
or ANO1 pin
Applying power
to and
disconnecting
power from
AV
AV
Reducing power
consumption in
STOP mode
REF1
REF0
Details of
Function
and
When a write operation is performed to the A/D converter mode register (ADM),
analog input channel specification register (ADS), and A/D port configuration register
(ADPC), the contents of ADCR and ADCRH may become undefined. Read the
conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion
result to be read.
The equivalent circuit of the analog input block is shown below (see Figure 11-28.).
Start the A/D converter after the AV
for the D/A converter) stabilize.
When setting the D/A converter, be sure to set DACEN to 1 first. If DACEN = 0,
writing to a control register of the D/A converter is ignored, and, even if the register is
read, only the default value is read (except for port mode register 11 (PM11) and port
register 11 (P11)).
Make the interval for writing DACSn of the same channel by one clock longer than
f
Make the interval for generating a start trigger to the same channel by one clock
longer than f
conversion will be performed only at the first trigger.
Note the following points in the procedure (i to iii) for outputting an arbitrary value in <3>.
• Do not generate the start trigger of the real-time output mode before enabling D/A
• An arbitrary value cannot be output in <3> if the DACEN bit of the PER0 register is
The digital port I/O function, which is the alternate function of the ANO0 and ANO1
pins, does not operate during D/A conversion.
During D/A conversion, 0 is read from the P11 register in input mode.
Do not read/write the P11 register and do not change the setting of the PM11 register
during D/A conversion (otherwise the conversion accuracy may decrease).
It is recommended that both the ANO0 and ANO1 pins be used as analog output pins
or digital I/O pins, that is, use these two channels for the same application (if these
pins are used for the different applications, the conversion accuracy may decrease).
In the real-time output mode, set the DACSn register value before the timer trigger is
generated. In addition, do not change the set value of the DACSn register while the
trigger signal is output.
Before changing the operation mode, be sure to clear the DACEn bit of the DAM
register to 0 (D/A conversion stop).
When using the port that functions alternately as the ANO0 or ANO1 pin, use it as the
port input with few level changes.
Stop the conversion performed by the D/A converter when supplying AV
AV
Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1
pins go into a high impedance state, and the power consumption can be reduced. In
the standby modes other than the STOP mode, however, the operation continues.
To lower the power consumption, therefore, clear the DACEn bit of the DAM register
to 0 (D/A conversion stop).
CLK
conversion operation in <3> after the value is set to the DACSn register in ii.
cleared once after the value is set to the DACSn register in ii.
REF0
. If writing is successively performed, only the value written last will be converted.
APPENDIX B LIST OF CAUTIONS
(the reference voltages for the A/D converter) starts or stops.
User’s Manual U18432EJ5V0UD
CLK
.
If a start trigger is successively generated for every f
REF0
Cautions
and AV
REF1
voltages (the reference voltages
CLK
REF1
, D/A
or
p.400
p.401
p.401
p.404
p.407
p.408
p.408
p.409
p.409
p.409
p.409
p.409
p.409
p.409
p.409
929
(17/35)
Page