UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 152

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.2.12 Port 12
mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-
chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
using port input mode register 12 (PIM12).
port output mode register 12 (POM12).
connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main
system clock, serial interface data I/O, and clock I/O.
150
Caution 1. The function setting on P121 to P124 is available only once after the reset release. The port
P120 and P125 to P127 are a 4-bit I/O port with an output latch. P120 and P125 to P127 can be set to the input
P121 to P124 are 4-bit input ports.
Input to the P125 and P126 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
Output from the P125 to P127 pins can be specified as N-ch open-drain output (V
This port can also be used for external interrupt request input, potential input for external low-voltage detection,
Reset signal generation sets port 12 to input mode.
Figures 4-38 to 4-42 show block diagrams of port 12.
WR
WR
WR
P12:
PU12:
PM12:
RD:
WR××: Write signal
RD
PORT
PU
PM
2. To use P125/SCK21/SCL21, P126/SI21/SDA21, or P127/SO21 as a general-purpose port, note
once set for connection to an oscillator cannot be used as an input port unless the reset is
performed.
the serial array unit 1 setting. For details, refer to Table 13-10 Relationship Between Register
Settings and Pins (Channel 1 of Unit 1: CSI21, UART2 reception, IIC21).
Port register 12
Pull-up resistor option register 12
Port mode register 12
Read signal
Output latch
Alternate
function
(P120)
PM120
PU120
PM12
PU12
P12
Figure 4-38. Block Diagram of P120
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18432EJ5V0UD
DD
EV
tolerance) in 1-bit units using
DD0
, EV
P-ch
DD1
P120/INTP0/EXLVI