UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 46

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Port mode
(2) Control mode
2.2.13 P130, P131 (port 13)
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P130 functions as a 1-bit output port. P131 functions as a 1-bit I/O port. P131 pin also function as timer I/O.
Remark When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before
P120 and P125 to P127 function as a 4-bit I/O port. P120 and P125 to P127 can be set to input or output port
using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 12 (PU12).
P121 to P124 function as a 4-bit input port.
P120 to P127 function as external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for
main system clock, serial interface data I/O, and clock I/O.
(a) INTP0
(b) EXLVI
(c) X1, X2
(d) EXCLK
(e) XT1, XT2
(f) SI21
(g) SO21
(h) SCK21
(i)
(j)
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
This is a potential input pin for external low-voltage detection.
These are the pins for connecting a resonator for main system clock.
This is an external clock input pin for main system clock.
These are the pins for connecting a resonator for subsystem clock.
This is a serial data input pin of serial interface CSI21.
This is a serial data output pin of serial interface CSI21.
This is a serial clock I/O pin of serial interface CSI21.
SDA21
This is a serial data I/O pin of serial interface for simplified I
SCL21
This is a serial clock I/O pin of serial interface for simplified I
the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the
figure for Remark in 4.2.13 Port 13).
CHAPTER 2 PIN FUNCTIONS
User’s Manual U18432EJ5V0UD
2
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