UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 708
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UPD78F1174AGF-GAT-AX
Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1174AGF-GAT-AX.pdf
(968 pages)
Specifications of UPD78F1174AGF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
706
(when X1 oscillation
oscillation clock (f
Internal reset signal
Internal high-speed
V
system clock (f
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
Remark V
POC
= 1.59 V (TYP.)
High-speed
is selected)
Supply voltage
1.8 V
CPU
2.
3.
4.
5.
MX
IH
(V
Note 1
V
)
)
0 V
Operation
LVI
LOW-VOLTAGE DETECTOR).
V
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
DD
The operation guaranteed range is 1.8 V ≤ V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.),
input a low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by
using an option byte (option byte: LVIOFF = 0).
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
)
stops
: LVI detection voltage
: POC detection voltage
Wait for oscillation
accuracy stabilization
specified by software.
Wait for voltage
Starting oscillation is
0.5 V/ms (MIN.)
stabilization
1.92 to 6.17 ms
Reset processing
Note 2
Set LVI to be
used for reset
Note 3
oscillation clock)
(internal high-speed
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Normal operation
and Low-Voltage Detector (1/2)
Note 5
User’s Manual U18432EJ5V0UD
Reset period
(oscillation
stop)
Reset processing (43 to 160 s)
Wait for oscillation
accuracy stabilization
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
DD
≤ 5.5 V. To make the state at lower than 1.8 V reset
Note 4
μ
Note 5
Reset period
(oscillation
stop)
Wait for voltage
Wait for oscillation
accuracy stabilization
specified by software.
stabilization
Starting oscillation is
1.92 to 6.17 ms
Reset processing
Set LVI to be
used for reset
Note 3
oscillation clock)
(internal high-speed
Normal operation
Note 5
Operation stops
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