UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 531

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
13.7.1 Address field transmission
for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are
transmitted in one frame.
Note To perform communication via simplified I
Remark
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data level
Parity bit
Stop bit
Data direction
Address field transmission is a transmission operation that first executes in I
Simplified I
POM96, POM126, POM143 = 1) for the port output mode registers (POM0, POM9, POM12, POM14) (see 4.3
Registers Controlling Port Function for details). When communicating with an external device with a
different potential, set the N-ch open-drain output (V
= 1) also for the clock input/output pins (SCL10, SCL11, SCL20, SCL21) (see 4.4.4 Connecting to external
device with different potential (2.5 V, 3 V) for details).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2
C
Channel 2 of SAU0
SCL10, SDA10
INTIIC10
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Parity error detection flag (PEFmn)
8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W
control)
Max. f
However, the following condition must be satisfied in each mode of I
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Forward output (default: high level)
No parity bit
Appending 1 bit (for ACK reception timing)
MSB first
MCK
IIC10
/4 [Hz] (SDRmn[15:9] = 1 or more)
Note
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U18432EJ5V0UD
Channel 3 of SAU0
SCL11, SDA11
INTIIC11
2
C, set the N-ch open-drain output (V
IIC11
DD
Note
tolerance) mode (POM04, POM95, POM125, POM142
f
MCK
: Operation clock (MCK) frequency of target channel
Channel 0 of SAU1
SCL20, SDA20
INTIIC20
2
IIC20
C communication to identify the target
2
C.
Note
DD
tolerance) mode (POM03,
Channel 1 of SAU1
SCL21, SDA21
INTIIC21
IIC21
Note
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