UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 255

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: F00F0H
(1) Peripheral enable register 0 (PER0)
Symbol
PER0
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
When the timer array unit 1 is used, be sure to set bit 1 (TAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
Remark m = 0, 1
TAUmEN
RTCEN
<7>
When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0, writing to
a control register of the timer array unit is ignored, and all read values are default values
(except for timer input select register m (TISm), input switch control register (ISC), noise
filter enable registers 1, 2 (NFEN1, NFFN2), port mode registers 0, 1, 3, 4, 13, 14, 16 (PM0,
PM1, PM3, PM4, PM13, PM14, PM16), and port registers 0, 1, 3, 4, 13, 14, 16 (P0, P1, P3, P4,
P13, P14, P16)).
0
1
After reset: 00H
Stops supply of input clock.
• SFR used by the timer array unit m cannot be written.
• The timer array unit m is in the reset status.
Supplies input clock.
• SFR used by the timer array unit m can be read/written.
Figure 7-5. Format of Peripheral Enable Register 0 (PER0)
DACEN
<6>
R/W
CHAPTER 7 TIMER ARRAY UNIT
ADCEN
<5>
User’s Manual U18432EJ5V0UD
Control of timer array unit m input clock
IIC0EN
<4>
SAU1EN
<3>
SAU0EN
<2>
TAU1EN
<1>
TAU0EN
<0>
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