UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 191

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.4 Number of Instruction Wait Clocks or Data Access
and the number of wait states.
5.5 Number of Instruction Execution Clocks and Instruction Wait Clocks for Fetch Access
interface every 16 bits. Consequently, it takes time about two times longer than the internal flash to capture an
instruction. Furthermore, a wait is inserted when accessing an external memory. Consequently, the minimum and
maximum numbers of execution clocks of each instruction when fetching instructions from the external memory are as
follows, for the number of clocks when instructions are fetched from the internal ROM (flash memory) area.
Wait clocks are added to the number of clocks of an instruction when the external bus interface is accessed.
The actual number of operating clocks is therefore the sum of the number of operating clocks of each instruction
The internal flash captures an opcode every 32 bits. However, an opcode is captured from the external bus
Furthermore, the number of waits is as follows, depending on the clock selected for the CLKOUT pin.
Remark 1 clock: 1/f
Caution The flash memory and external memory are located in consecutive spaces, but start
Remark 1 clock: 1/f
Note Number of clocks when the internal RAM area, SFR area, or expanded SFR area has been
No. of Instruction Execution Clocks
When Fetching Instructions from
fetching in the external memory space by using a branch instruction (CALL, BR) in the
flash memory or RAM memory.
accessed, or when an instruction that does not access data is executed
Internal ROM Area
f
f
f
f
f
f
f
f
CLK
CLK/
CLK
CLK
CLK
CLK
CLK
CLK
CLKOUT Pin Selection Clock
CLKOUT Pin Selection Clock
CLK
CLK
/3
/4
/2
/3
/4
2
1
2
3
4
5
6
(f
(f
CHAPTER 5 EXTERNAL BUS INTERFACE
CLK
CLK
: CPU clock)
: CPU clock)
Note
User’s Manual U18432EJ5V0UD
When Fetching Instructions from External Memory
Execution Clocks
Minimum No. of
10 + 5 × Wait
2 + 2 × Wait
6 + 2 × Wait
4 + 2 × Wait
8 + 2 × Wait
6 + 2 × Wait
3 clocks
5 or 6 clocks
7 to 9 clocks
9 to 12 clocks
Number of Wait States (Fetch)
3 clocks
5 or 6 clocks
7 to 9 clocks
9 to 12 clocks
Number of Waits States
(Read/Write)
Execution Clocks
Maximum No. of
10 + 10 × Wait
14 + 11 × Wait
12 + 9 × Wait
5 + 3 × Wait
7 + 6 × Wait
8 + 8 × Wait
189