UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 532

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

530
(1) Register setting
SMRmn
SCRmn
SDRmn
SOEm
SOm
SSm
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel.
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
(d) Serial mode register mn (SMRmn)
(e) Serial communication operation setting register mn (SCRmn)
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
Remark
Figure 13-93. Example of Contents of Registers for Address Field Transmission of Simplified I
CKSmn
TXEmn
0/1
15
15
15
15
15
15
0
0
0
1
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 10, 11, 20, 21)
0/1: Set to 0 or 1 depending on the usage of the user
CCSmn
RXEmn
14
14
14
14
14
14
0
0
0
0
0
: Setting is fixed in the IIC mode,
DAPmn
13
13
13
13
13
13
0
0
0
0
0
Baud rate setting
Setting of parity bit
00B: No parity
CKPmn
12
12
12
12
12
12
0
0
0
0
0
CKOm3
0/1
11
11
11
11
11
11
0
0
0
0
CHAPTER 13 SERIAL ARRAY UNIT
CKOm2
EOCmn
0/1
10
10
10
10
10
10
0
0
0
0
(IIC10, IIC11, IIC20, IIC21)
User’s Manual U18432EJ5V0UD
CKOm1
PTCmn1
0/1
Start condition is generated by manipulating the SOmn bit.
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
9
9
0
9
0
9
0
9
0
9
PTCmn0
CKOm0
STSmn
0/1
: Setting disabled (set to the initial value)
8
0
8
0
8
8
0
8
0
8
0
DIRmn
0
0
7
0
7
7
0
7
0
7
7
SISmn0
0
0
0
6
0
0
6
6
6
6
6
Transmit data setting (address + R/W)
SLCmn1
0
5
0
0
0
5
1
5
5
5
5
SLCmn0
Interrupt sources of channel n
0: Transfer end interrupt
4
0
0
4
0
4
1
4
0
4
4
SIOr
SOEm3
SOm3
SSm3
0/1
0/1
0/1
Setting of stop bit
01B: Appending 1 bit
3
0
3
0
3
3
3
3
SOEm2
MDmn2
DLSmn2
SOm2
SSm2
0/1
0/1
0/1
1
2
1
2
2
2
2
2
SOEm1
MDmn1
DLSmn1
SOm1
SSm1
0/1
0/1
0/1
0
1
1
1
1
1
1
1
MDmn0
DLSmn0
SOEm0
SOm0
SSm0
0/1
0/1
0/1
0
0
0
0
1
0
0
0
2
C