UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 282

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

280
Master channel
Slave channel
(b) Set/reset timing
Remarks 1. to_reset: TOmn pin reset/toggle signal
To realize 0%/100% output at PWM output, the TOmn pin/TOmn set timing at master channel timer
interrupt (INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the
latter.
Figure 7-31 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0
Slave channel:
(Internal signal)
(Internal signal)
(Internal signal)
2. m: Unit number, n: Channel number, p: Slave channel number
Count clock
TOmn pin/
TOmp pin/
INTTMmn
INTTMmp
to_set:
When m = 0
When m = 1
to_reset
to_reset
to_set
n = 0 to 7 (n = 0, 2, 4, 6 for master channel)
n < p ≤ 7 (where p is a consecutive integer greater than n)
n = 0 to 3 (n = 0, 2 for master channel)
n < p ≤ 3 (where p is a consecutive integer greater than n)
TOmn
TOmp
f
CLK
TOmn pin set signal
Figure 7-31. Set/Reset Timing Operating Statuses
TOEmp = 1, TOMmp = 1, TOLmp = 0
Delays to_reset by 1 count
clock with slave channel
CHAPTER 7 TIMER ARRAY UNIT
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User’s Manual U18432EJ5V0UD
Set
Reset