UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 175

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.4.4 Connecting to external device with different potential (2.5 V, 3 V)
that operates on 2.5 V or 3 V power supply voltage are possible.
PIM9, PIM12, PIM14).
drain (V
(1) Setting procedure when using I/O pins of UART1, UART2, CSI01, CSI10, CSI11, CSI20 and CSI21 functions
When parts of ports 0, 4, 9, 12 and 14 operate with V
Regarding inputs, CMOS/TTL switching is possible on a bit-by-bit basis by port input mode registers (PIM0, PIM4,
Moreover, regarding outputs, different potentials can be supported by switching the output buffer to the N-ch open
(a) Use as 2.5 V or 3 V input port
(b) Use as 2.5 V or 3 V output port
DD
withstand voltage) by the port output mode registers (POM0, POM4, POM9, POM12, POM14).
<1> After reset release, the port mode is the input mode (Hi-Z).
<2> If pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
<3> Set the corresponding bit of the PIMn register to 1 to switch to the TTL input buffer.
<4> V
<1> After reset release, the port mode changes to the input mode (Hi-Z).
<2> Pull up externally the pin to be used (on-chip pull-up resistor cannot be used).
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POMn register to 1 to set the N-ch open drain output (V
<5> Set the output mode by manipulating the PMn register.
<6> Operation is done only in the low level according to the operating status of the serial array unit.
At this time, the output data is high level, so the pin is in the Hi-Z state.
Remark n = 0, 4, 9, 12, 14
voltage) mode.
IH
/V
IL
In case of UART1:
In case of UART2:
In case of CSI01:
In case of CSI10:
In case of CSI11:
In case of CSI20:
In case of CSI21:
operates on 2.5 V or 3 V operating voltage.
In case of UART1:
In case of UART2:
In case of CSI01:
In case of CSI10:
In case of CSI11:
In case of CSI20:
In case of CSI21:
CHAPTER 4 PORT FUNCTIONS
P03
P143
P43, P44
P03, P04
P95, P96
P142, P143
P125, P126
P02
P144
P43, P45
P02, P04
P95, P97
P142, P144
P125, P127
User’s Manual U18432EJ5V0UD
DD
= 4.0 V to 5.5 V, I/O connections with an external device
DD
withstand
173