UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 422

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

420
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1)
Symbol
SPSm
Notes1. When changing the clock selected for f
Cautions 1. Be sure to clear bits 15 to 8 to “0”.
Remarks 1. f
2. SAU0 can be operated at a fixed division ratio of the subsystem clock, regardless of the f
PRS
mp3
15
0
0
0
0
0
0
0
0
1
1
1
1
1
0
value), do so after having stopped (STm = 000FH) the operation of the serial array unit (SAU). When
selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit 0 (TAU0) (TT0
= 00FFH).
frequency (main system clock, subsystem clock), by operating the interval timer for which f
been selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1)
and selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU. When
changing f
2. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
2. m: Unit number (m = 0, 1), p = 0, 1
Other than above
PRS
mp2
clocks have elapsed.
f
14
CLK
SUB
0
0
0
0
1
1
1
1
0
0
0
0
1
0
: CPU/peripheral hardware clock frequency
: Subsystem clock frequency
Figure 13-5. Format of Serial Clock Select Register m (SPSm)
CLK
PRS
mp1
13
0
0
1
1
0
0
1
1
0
0
1
1
1
0
, however, SAU and TAU0 must be stopped as described in Note 1 above.
PRS
mp0
12
0
1
0
1
0
1
0
1
0
1
0
1
1
0
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0, INTTM03 if m = 1
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CHAPTER 13 SERIAL ARRAY UNIT
11
0
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
User’s Manual U18432EJ5V0UD
10
0
9
0
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
15.6 kHz
7.81 kHz
3.91 kHz
1.95 kHz
977 Hz
f
CLK
CLK
After reset: 0000H
= 2 MHz
8
0
Section of operation clock (CKmp)
(by changing the system clock control register (CKC)
PRS
m13
7
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
4.88 kHz
2.44 kHz
Note 2
f
PRS
m12
CLK
6
= 5 MHz
R/W
PRS
m11
5
PRS
m10
5 MHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
4.88 kHz
10 MHz
2.5 MHz
1.25 MHz
625 kHz
4
f
CLK
= 10 MHz
Note 1
PRS
m03
3
PRS
m02
2
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
f
CLK
PRS
m01
= 20 MHz
1
SUB
/4 has
PRS
m00
0
CLK