UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 920

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

918
Clock
generator
Function
OSTS:
Oscillation
stabilization time
select register
CKC: System
clock control
register
PER0, PER1:
Peripheral enable
registers 0, 1
OSMC:
Operation speed
mode control
register
HIOTRM:
Internal high-
speed oscillator
trimming register
Details of
Function
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
Be sure to set bit 3 to 1.
The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and
peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to
peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer) is also changed at the same time.
peripheral function when changing the CPU/peripheral operating hardware clock.
If the peripheral hardware clock is used as the subsystem clock, the operations of the
A/D converter and IIC0 are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
Be sure to clear bits 1 to 7 of the PER1 register to 0.
OSMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing f
• Operating the DMA controller.
The CPU waits when “1” is written to the FSEL flag.
Interrupt requests issued during a wait will be suspended.
The wait time is 16.6
f
while the CPU is waiting.
To increase f
more clocks have elapsed. Use the external bus interface two clock cycles after
setting FSEL to 1.
Flash memory can be used at a frequency of 10 MHz or lower if FSEL is 1.
The frequency will vary if the temperature and V
adjustment.
Moreover, if the HIOTRM register is set to any value other than the initial value (10H),
the oscillation accuracy of the internal high-speed oscillation clock may exceed 8
MHz±5%, depending on the subsequent temperature and V
HIOTRM register setting. When the temperature and V
adjustment must be executed regularly or before the frequency accuracy is required.
The
increasing/decreasing the HIOTRM value to a value larger/smaller than a certain
value.
increasing/decreasing the HIOTRM value does not occur.
IH
/2. However, counting the oscillation stabilization time of f
well
internal
APPENDIX B LIST OF CAUTIONS
A
as
User’s Manual U18432EJ5V0UD
reversal,
CLK
CHAPTER
high-speed
to 10 MHz or higher, set FSEL to “1”, then change f
μ
s to 18.5
such
29
oscillation
as
μ
s when f
ELECTRICAL
the
CLK
Cautions
to a clock other than f
CLK
frequency
frequency
= f
IH
DD
, and 33.3
SPECIFICATIONS
pin voltage change after accuracy
becoming
becomes
DD
Consequently, stop each
voltage change, accuracy
μ
s to 36.9
IH
DD
X
.
voltage change, or
can continue even
faster/slower
slower/faster
CLK
μ
(STANDARD
s when f
after two or
CLK
by
by
=
p.211
p.213
p.213
p.213
pp.214,
215
p.216
p.216
p.216
p.216
p.216
p.217
p.218
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