UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 957

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2nd edition
Edition
Change of Figure 13-36. Timing Chart of Master Reception (in Single-Reception
Mode)
Change of Figure 13-41. Procedure for Resuming Master
Transmission/Reception
Change of Figure 13-42. Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode)
Change of Figure 13-44. Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 13-45. Flowchart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 13-49. Procedure for Resuming Slave Transmission
Change of Figure 13-50. Timing Chart of Slave Transmission (in Single-
Transmission Mode)
Change of Figure 13-57. Procedure for Resuming Slave Reception
Change of Figure 13-58. Timing Chart of Slave Reception (in Single-Reception
Mode)
Change of Figure 13-63. Procedure for Resuming Slave
Transmission/Reception
Change of Figure 13-64. Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode)
Change of Figure 13-66. Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 13-67. Flowchart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Note in 13.5.7 (2)
Addition of setting and Note to Table 13-2. Operating Clock Selection
Change of transfer rate and addition of Note
Change of Transfer data length in 13.6.2 UART reception
Change of setting of (b) Serial output enable register m (SOEm) and (e) Serial
mode register mr (SMRmr) in Figure 13-76. Example of Contents of Registers
for UART Reception of UART (UART0, UART1, UART2, UART3)
Change of Figure 13-79. Timing Chart of UART Reception
Change of Transfer data length in 13.6.3 LIN transmission
Change of Transfer data length in 13.6.4 LIN reception
Addition of setting and Note to Table 13-3. Operating Clock Selection
Change of Figure 13-89. Initial Setting Procedure for Address Field
Transmission
Change of Figure 13-90. Timing Chart of Address Field Transmission
Change of Figure 13-91. Flowchart of Address Field Transmission
Change of Figure 13-92. Example of Contents of Registers for Data
Transmission of Simplified I
Change of Figure 13-94. Flowchart of Data Transmission
Change of Figure 13-95. Example of Contents of Registers for Data Reception
of Simplified I
Change of Figure 13-96. Timing Chart of Data Reception
Change of Figure 13-97. Flowchart of Data Reception and addition of Caution
2
C (IIC10, IIC11, IIC20, IIC21) and addition of Note
APPENDIX C REVISION HISTORY
2
C (IIC10, IIC11, IIC20, IIC21) and addition of Note
User’s Manual U18432EJ5V0UD
Description
CHAPTER 13 SERIAL
ARRAY UNIT
Chapter
(3/13)
955