UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 936

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

934
DMA
controller
Interrupt
functions
Function
DRCn: DMA
operation control
register n
Example of
setting for
holding DMA
transfer pending
by DWAITn
Forced
termination of
DMA Transfer
Priority
Response time
Operation in
standby mode
DMA pending
instruction
Operation if
address in
general-purpose
register area or
other than those
of internal RAM
area is specified
IF0L, IF0H, IF1L,
IF1H, IF2L, IF2H:
Interrupt request
flag registers
Details of
Function
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is
terminated without waiting for generation of the interrupt (INTDMAn) of DMAn,
therefore, set DSTn to 0 and then DENn to 0 (for details, refer to 16.5.5 Forcible
termination by software).
When DMA transfer is held pending while using both DMA channels, be sure to hold
the DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1). If
the DMA transfer of one channel is executed while that of the other channel is held
pending, DMA transfer might not be held pending for the latter channel.
In example 3, the system is not required to wait two clock cycles after DWAITn is set
to 1. In addition, the system does not have to wait two clock cycles after clearing
DSTn to 0, because more than two clock cycles elapse from when DSTn is cleared to
0 to when DENn is cleared to 0.
During DMA transfer, a request from the other DMA channel is held pending even if
generated. The pending DMA transfer is started after the ongoing DMA transfer is
completed. If two DMA requests are generated at the same time, however, DMA
channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA
transfer takes precedence, and then interrupt servicing is executed.
The response time of DMA transfer is as follows. (See Table 16-2.)
The DMA controller operates as follows in the standby mode. (See Table 16-3.)
Even if a DMA request is generated, DMA transfer is held pending immediately after
the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L,
The address indicated by DRA0n is incremented during DMA transfer. If the address
is incremented to an address in the general-purpose register area or exceeds the
area of the internal RAM, the following operation is performed.
In either case, malfunctioning may occur or damage may be done to the system.
Therefore, make sure that the address is within the internal RAM area other than the
general-purpose register area.
Be sure to clear bits 5 to 7 of IF2H to 0.
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag may
be set by noise.
MK0H, MK1L, MK1H, MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L,
PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H and PSW each.
In mode of transfer from SFR to RAM
The data of that address is lost.
In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
Cautions
p.637
p.650
p.652
p.652
p.653
p.654
p.654
p.654
p.664
p.664
(22/35)
Page