UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 261

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UPD78F1174AGF-GAT-AX

Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1174AGF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07)
(4) Timer status register mn (TSRmn)
TSRmn
Symbol
TSRmn indicates the overflow status of the counter of channel n.
TSRmn is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3
to MDmn1 = 110B). It will not be set in any other mode. See Table 7-3 for the operation of the OVF bit in each
operation mode and set/clear conditions.
TSRmn can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TSRmn can be set with an 8-bit memory manipulation instruction with TSRmnL.
Reset signal generation clears this register to 0000H.
Remark
F01D0H, F01D1H (TSR10) to F01D6H, F01D7H (TSR13)
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
• Capture mode
• Capture & one-count mode
• Interval timer mode
• Event counter mode
• One-count mode
OVF
Remark
15
0
1
0
Table 7-3. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
Timer operation mode
Overflow does not occur.
Overflow occurs.
14
0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7),
mn = 00 to 07, 10 to 13
13
Figure 7-8. Format of Timer Status Register mn (TSRmn)
0
12
0
11
0
CHAPTER 7 TIMER ARRAY UNIT
clear
set
clear
set
OVF
User’s Manual U18432EJ5V0UD
10
0
When no overflow has occurred upon capturing
When an overflow has occurred upon capturing
Counter overflow status of channel n
9
0
8
0
After reset: 0000H
(Use prohibited, not set and not cleared)
7
0
6
0
Set/clear conditions
5
0
R
4
0
3
0
2
0
1
0
OVF
259
0

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