UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 264

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

262
(a) Start timing in interval timer mode
Caution In the first cycle operation of count clock after writing TSmn, an error at a maximum of one
<1> Writing 1 to TSmn sets TEmn = 1
<2> The write data to TSmn is held until count clock generation.
<3> TCRmn holds the initial value until count clock generation.
<4> On generation of count clock, the “TDRmn value” is loaded to TCRmn and count starts.
Table 7-4. Operations from Count Operation Enabled State to TCRmn Count Start (2/2)
• One-count mode
• Capture & one-count mode
Start trigger detection signal
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start
by setting MDmn0 = 1.
Timer operation mode
TSmn (write) hold signal
TSmn (write)
Count clock
INTTMmn
TCRmn
Figure 7-11. Start Timing (In Interval Timer Mode)
TEmn
f
CLK
CHAPTER 7 TIMER ARRAY UNIT
<1>
When TSmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 7.3 (6) (d) Start timing in one-
count mode).
When TSmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 7.3 (6) (e) Start timing in capture & one-
count mode).
User’s Manual U18432EJ5V0UD
<2>
Initial value
<3>
Operation when TSmn = 1 is set
TDRmn value
When MDmn0 = 1 is set
<4>