UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 927

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Watchdog
timer
Clock
output/
buzzer
output
controller
A/D
converter
Function
Setting window
open period
Setting interval
interrupt
CKSn: Clock
output select
registers n
PER0:
Peripheral
enable register 0
ADM: A/D
converter mode
register
A/D conversion
time selection
(2.7 V ≤ AV
5.5 V)
A/D conversion
time selection
(2.3 V ≤ AV
5.5 V)
Details of
Function
REF0
REF0
≤
≤
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU
starts operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing a
reset.
When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period
is 100% regardless of the values of WINDOW1 and WINDOW0.
Do not set the window open period to 25% if the watchdog timer corresponds to
either of the conditions below.
• When used at a supply voltage (V
• When stopping all main system clocks (internal high-speed oscillation clock, X1
• Low-power consumption mode
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
Change the output clock after disabling clock output (PCLOEn = 0).
If the selected clock (f
becomes undefined.
When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0,
writing to a control register of the A/D converter is ignored, and, even if the register is
read, only the default value is read (except for port mode registers 2 and 15 (PM2,
PM15)).
A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to
values other than the identical data.
Set the conversion times with the following conditions.
Conventional-specification products (
• 4.0 V ≤ AV
• 2.7 V ≤ AV
Functionally expanded products (
• 4.0 V ≤ AV
• 2.7 V ≤ AV
Set the conversion times with the following conditions.
• 4.0 V ≤ AV
• 2.7 V ≤ AV
• 2.3 V ≤ AV
When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D
conversion once (ADCS = 0) beforehand.
Change LV1 and LV0 from the default value, when 2.3 V ≤ AV
The above conversion time does not include clock frequency errors.
conversion time, taking clock frequency errors into consideration.
clock, and external main system clock) by use of the STOP mode or software.
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
REF0
REF0
REF0
REF0
REF0
REF0
REF0
≤ 5.5 V: f
< 4.0 V: f
≤ 5.5 V: f
< 4.0 V: f
≤ 5.5 V: f
< 4.0 V: f
< 2.7 V: f
MAIN
AD
AD
AD
AD
AD
AD
AD
or f
= 0.6 to 3.6 MHz
= 0.6 to 1.8 MHz
= 0.33 to 3.6 MHz
= 0.33 to 1.8 MHz
= 0.6 to 3.6 MHz
= 0.6 to 1.8 MHz
= 0.6 to 1.44 MHz
SUB
) stops during clock output (PCLOEn = 1), the output
μ
PD78F117xA)
DD
μ
) below 2.7 V.
Cautions
PD78F117x)
REF0
< 2.7 V.
Select
p.364
p.364
p.365
p.368
p.368
p.373
p.374
p.375
p.376
p.376
p.376
p.376
(13/35)
925
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