UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 951

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark “Classification” in the above table classifies revisions as follows.
CHAPTER 7 TIMER ARRAY UNIT
p.247
p.264
p.265
p.272
CHAPTER 8 REAL-TIME COUNTER
p.331
p.333
p.335
p.340
p.340
p.345
p.347
p.348
p.353
p.353
p.353
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
p.369
p.369
CHAPTER 11 A/D CONVERTER
p.374
p.374
p.397
p.401
CHAPTER 12 D/A CONVERTER
p.409
p.409
CHAPTER 13 SERIAL ARRAY UNIT
p.422
p.424
p.426
p.436
p.454
p.455
p.457
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Change of Figure 7-1. Block Diagram of Timer Array Unit
Change of Figure 7-14. Start Timing (In One-count Mode)
Change of Figure 7-15. Start Timing (In Capture & One-count Mode)
Change of description of ISC1 and ISC0 bits in Figure 7-22. Format of Input Switch Control
Register (ISC)
Change of Table 8-1. Configuration of Real-Time Counter
Change of 8.3 Registers Controlling Real-Time Counter
Change of description of AMPM bit in Figure 8-3. Format of Real-Time Counter Control
Register 0 (RTCC0)
Change of description of 8.3 (7) Minute count register (MIN)
Change of description of 8.3 (8) Hour count register (HOUR)
Addition of description of DEV bit to Figure 8-14. Format of Watch Error Correction Register
(SUBCUD)
Addition of 8.3 (17) Port mode registers 1, 3 (PM1, PM3)
Change of Figure 8-19. Procedure for Starting Operation of Real-Time Counter and addition of
Note
Addition of Caution to 8.4.5 1 Hz output of real-time counter
Change of 8.4.6 32.768 kHz output of real-time counter
Change of 8.4.7 512 Hz, 16.384 kHz output of real-time counter
Change of Remark in 10.4.1 Operation as output pin
Change of Figure 10-4. Remote Control Output Application Example
Change of Table 11-2. Settings of ADCS and ADCE
Change of Figure 11-5. Timing Chart When A/D voltage Comparator Is Used
Change of 11.7 Cautions for A/D Converter (2) Reducing current when A/D converter is
stopped
Addition of 11.7 (13) Starting the A/D converter
Change of 12.4.3 Cautions (1)
Change of 12.4.3 Cautions (7)
Change of MDmn0 bit in Figure 13-6. Format of Serial Mode Register mn (SMRmn) (2/2)
Addition of Note to Figure 13-7. Format of Serial Communication Operation Setting Register
mn (SCRmn) (2/3)
Addition of Caution to Figure 13-8. Format of Serial Data Register mn (SDRmn)
Change of description of Figure 13-17. Format of Input Switch Control Register (ISC)
Change of interrupt in 13.5.2 Master reception
Change of Figure 13-32. Example of Contents of Registers for Master Reception of 3-Wire
Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21)
Change of Figure 13-35. Procedure for Resuming Master Reception
APPENDIX C REVISION HISTORY
User’s Manual U18432EJ5V0UD
Description
Classification
(a)
(a)
(a)
(a)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
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(2/5)
949