UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 192

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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5.6 Number of Instructed Wait Cycles According to External Wait Cycles
low-level signal
is inserted.
pin at the rising edge of the CLKOUT signal for the second time in a row, a wait cycle of two CLKOUT clock cycles
occurs. Therefore, the number of external wait cycles in 1/f
190
If an external device that has a low access speed is accessed, wait cycles can be inserted into the bus cycle. If a
For example, if f
CLKOUT
(= f
Note
Remarks 1.
Figure 5-4. Example in Which External Wait Cycles Are Inserted When Separate Bus Is Read
CLK
WAIT
f
RD
CLK
/3)
Note
is input to the WAIT pin at the rising edge of the CLKOUT signal, a wait of one CLKOUT clock cycle
CLK
The WAIT setup time from CLKOUT ↑ (t
electrical specifications must be satisfied(see CHAPTER 29 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
2.
/3 is selected as the clock signal for the CLKOUT pin, and a low-level signal is input to the WAIT
1 clock: 1/f
The broken line in Figure 5-4 shows the waveform of the signal output from the RD pin if no
external wait cycle occurred.
CLK
CHAPTER 5 EXTERNAL BUS INTERFACE
(f
CLK
: CPU clock)
User’s Manual U18432EJ5V0UD
CLK
SKWT1
External Wait = (1/CLKOUT)
units is six clock cycles (see Figure 5-4).
) and WAIT hold time from CLKOUT ↑ (t
Wait
×
2 = (1/f
Wait
CLK
)
×
6
HKWT1
) in the