UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 263

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: F01B2H, F01B3H
Address: F01DAH, F01DBH
(6) Timer channel start register m (TSm)
Symbol
Symbol
TS0
TS1
TSm is a trigger register that is used to clear a timer counter (TCRmn) and start the counting operation of each
channel.
When a bit (TSmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status
register m (TEm) is set to 1. TSmn is a trigger bit and cleared immediately when TEmn = 1.
TSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TSm can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 15 to 8 of TS0 and bits 15 to 4 of TS1 to “0”
Remarks 1. When the TSm register is read, 0 is always read.
Table 7-4. Operations from Count Operation Enabled State to TCRmn Count Start (1/2)
• Interval timer mode
• Event counter mode
• Capture mode
TS
mn
15
15
0
1
0
0
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7),
Timer operation mode
No trigger operation
TEmn is set to 1 and the count operation becomes enabled.
The TCRmn count operation start in the count operation enabled state varies depending on each operation
mode (see Table 7-4).
mn = 00 to 07, 10 to 13
14
14
0
0
Figure 7-10. Format of Timer Channel Start Register m (TSm)
After reset: 0000H
13
13
After reset: 0000H
0
0
12
12
0
0
11
11
0
0
CHAPTER 7 TIMER ARRAY UNIT
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 7.3 (6) (a) Start timing in
interval timer mode).
Writing 1 to TSmn bit loads the value of TDRmn to TCRmn.
The subsequent count clock performs count down operation.
The external trigger detection selected by STSmn2 to STSmn0 bits in the
TMRmn register does not start count operation (see 7.3 (6) (b) Start timing in
event counter mode).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 7.3 (6) (c) Start timing in capture mode).
User’s Manual U18432EJ5V0UD
R/W
R/W
10
10
0
0
Operation enable (start) trigger of channel n
9
0
9
0
8
0
8
0
Operation when TSmn = 1 is set
TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
7
7
0
6
6
0
5
5
0
4
4
0
TS13 TS12 TS11 TS10
3
3
2
2
1
1
261
0
0