UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 520

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.6.4 LIN reception
518
Support of LIN communication
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
Of UART reception, UART3 supports LIN communication.
For LIN reception, channel 3 of unit 1 (SAU1) is used.
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the
Remark f
Figure 13-87 outlines a reception operation of LIN.
electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
UART
f
MCK
CLK
: System clock frequency
: Operation clock (MCK) frequency of target channel
Not supported
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
• Framing error detection flag (FEF13)
• Parity error detection flag (PEF13)
• Overrun error detection flag (OVF13)
8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
UART0
/6 [bps] (SDR13 [15:9] = 2 or more), Min. f
−
−
−
−
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U18432EJ5V0UD
Not supported
UART1
−
−
−
−
Not supported
CLK
/(2 × 2
UART2
−
−
−
−
11
× 128) [bps]
Supported
Channel 0 of SAU1
RxD3
INTSR3
INTSRE3
Note
UART3