DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 998

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
18.6
In the I
address or the R/W bit, and the acknowledge bit may indicate the end of reception or reception of
the final frame, the continuous transfer of data by the DTC must be performed combined with the
CPU processing by the interrupt.
Table 18.5 shows some example of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 18.5 Example of Processing Using DTC
Rev. 3.00 May 17, 2007 Page 940 of 1582
REJ09B0181-0300
Item
Slave address +
R/W bit
transmission/
reception
Dummy data read 
Actual data
transmission/
reception
Last frame
processing
Setting of number
of DTC transfer
data frames
2
C bus format, since the slave device or the direction of transfer is selected by the slave
Operation Using the DTC
2
C Bus Interface 2 (I
Master Transmit
Mode
Transmission by
DTC (ICDR write)
Transmission by
DTC (ICDR write)
Not necessary
Transmission:
Actual data count
+ 1 (+ 1 equivalent
to slave address +
R/W bits)
2
C2)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by DTC
(ICDR read)
Reception by CPU
(ICDR read)
Reception: Actual
data count
Slave Transmit
Mode
Reception by CPU
(ICDR read)

Transmission by
DTC (ICDR write)
Not necessary
Transmission:
Actual data count
Slave Receive
Mode
Reception by CPU
(ICDR read)

Reception by DTC
(ICDR read)
Reception by CPU
(ICDR read)
Reception: Actual
data count