DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 333

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9.4.5
RTCSR specifies various items about refresh for SDRAM.
When writing to RTCSR, write data with setting the upper 16 bits to H'A55A to cancel write
protection.
Phase matching of the clock input to the refresh timer counter (RTCNT) is only performed on
power-on reset. Accordingly, if the timer is started with CKS[2:0] set to other than B'000, there
will be an error contained in the period until the first setting of the compare match flag.
Initial value:
Initial value:
Bit
31 to
16
15 to 8 
7
R/W:
R/W:
Bit:
Bit:
Bit Name

CMF
R/W
Refresh Timer Control/Status Register (RTCSR)
31
15
R
0
0
-
-
R/W
30
14
R
0
0
-
-
R/W
Initial
Value
All 0
All 0
0
29
13
R
0
0
-
-
R/W
28
12
R
0
0
-
-
R/W
R/W
R/W
R
R/W
27
11
R
0
0
-
-
R/W
26
10
R
0
0
-
-
Description
Write Protect Cancellation
When writing to RTCSR, write H'A55A to these bits to
cancel write protection. These bits are always read as 0.
Reserved
These bits are always read as 0. The write value should
always be 0.
Compare Match Flag
This is a status flag which indicates that a compare match
occurs between the refresh timer counter (RTCNT) and
refresh time constant register (RTCOR). This bit is set or
cleared in the following conditions.
0: Clearing condition: When 0 is written in CMF after
1: Setting condition: When the condition RTCNT =
R/W
reading out RTCSR during CMF = 1.
RTCOR is satisfied.
25
R
0
9
0
-
-
R/W
24
R
0
8
0
-
-
R/W
R/W
CMF
23
0
7
0
-
CMIE
R/W
R/W
Rev. 3.00 May 17, 2007 Page 275 of 1582
22
0
6
0
-
Section 9 Bus State Controller (BSC)
R/W
R/W
21
0
5
0
-
CKS[2:0]
R/W
R/W
20
0
4
0
-
R/W
R/W
19
0
3
0
-
REJ09B0181-0300
R/W
R/W
18
0
2
0
-
RRC[2:0]
R/W
R/W
17
0
1
0
-
R/W
R/W
16
0
0
0
-