DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1033

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The
CMT has a16-bit counter, and can generate interrupts at set intervals.
20.1
• Selection of four counter input clocks
• Interrupt request on compare match
• Module standby mode can be set.
Figure 20.1 shows a block diagram of CMT.
TIMCMT3A_000020030900
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected independently
for each channel.
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
Features
Control circuit
Compare match timer start register
Compare match timer control/status register
Compare match timer constant register
Compare match counter
Compare match interrupt
Section 20 Compare Match Timer (CMT)
CMI0
Pφ/8
Figure 20.1 Block Diagram of CMT
Clock selection
Pφ/32
Channel 0
Pφ/128
Module bus
CMT
Pφ/512
Control circuit
CMI1
Rev. 3.00 May 17, 2007 Page 975 of 1582
Section 20 Compare Match Timer (CMT)
Pφ/8
Clock selection
Pφ/32
Channel 1
Pφ/128
Internal bus
Pφ/512
REJ09B0181-0300
interface
Bus

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