DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 152
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Exception Handling
5.3.2
When an address error exception is generated, the bus cycle which caused the address error ends,
the current instruction finishes, and then the address error exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address
3. The start address of the exception handling routine is fetched from the exception handling
Rev. 3.00 May 17, 2007 Page 94 of 1582
REJ09B0181-0300
of the instruction which caused an address error exception. When the instruction that caused
the exception is placed in the delay slot, the address of the delayed branch instruction which is
placed immediately before the delay slot.
vector table that corresponds to the generated address error, and the program starts executing
from that address. This branch is not a delayed branch.
Address Error Exception Source
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