DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 767

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 13 Port Output Enable (POE)
13.4.3
Release from High-Impedance State
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the flags in bits 12 to 15 (POE0F to POE8F) of ICSR1 to ICSR3. However, note that when low-
level sampling is selected by bits 0 to 7 in ICSR1 to ICSR3, just writing 0 to a flag is ignored (the
flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to the
POE pin and is sampled.
High-current pins that have entered high-impedance state due to output-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing the flag
in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is
ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the
high-current pins. Inactive-level outputs can be achieved by setting the MTU2 and MTU2S
internal registers.
Rev. 3.00 May 17, 2007 Page 709 of 1582
REJ09B0181-0300