DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 101

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.5.2
Table 2.11 Data Transfer Instructions
Instruction
MOV
MOV.W @(disp,PC),Rn
MOV.L @(disp,PC),Rn
MOV
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B Rm,@–Rn
MOV.W Rm,@–Rn
MOV.L Rm,@–Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L @(disp,Rm),Rn
#imm,Rn
Rm,Rn
Data Transfer Instructions
Operation
imm → Sign extension
→ Rn
(disp × 2 + PC) → Sign
extension → Rn
(disp × 4 + PC) → Rn
Rm → Rn
Rm → (Rn)
Rm → (Rn)
Rm → (Rn)
(Rm) → Sign extension
→ Rn
(Rm) → Sign extension
→ Rn
(Rm) → Rn
Rn–1 → Rn, Rm → (Rn)
Rn–2 → Rn, Rm → (Rn)
Rn–4 → Rn, Rm → (Rn)
(Rm) → Sign extension
→ Rn, Rm + 1 → Rm
(Rm) → Sign extension
→ Rn, Rm + 2 → Rm
(Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110
R0 → (disp + Rn)
R0 → (disp × 2 + Rn)
Rm → (disp × 4 + Rn)
(disp + Rm) → Sign
extension → R0
(disp × 2 + Rm) → Sign
extension → R0
(disp × 4 + Rm) → Rn
Code
1110nnnniiiiiiii
1001nnnndddddddd
1101nnnndddddddd
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
0110nnnnmmmm0001
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
0110nnnnmmmm0101
10000000nnnndddd
10000001nnnndddd
0001nnnnmmmmdddd
10000100mmmmdddd
10000101mmmmdddd
0101nnnnmmmmdddd
Rev. 3.00 May 17, 2007 Page 43 of 1582
Execution
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
REJ09B0181-0300
Section 2 CPU
T Bit





















