DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 338

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Rev. 3.00 May 17, 2007 Page 280 of 1582
REJ09B0181-0300
Bit
14
13
12
Bit Name
CSSTP1

CSSTP2
Initial
Value
0
0
0
R/W
R/W
R
R/W
Description
Select Bus Release on NOP Cycle Generation by DTC
Specifies whether or not the bus is released in response
to requests from the CPU for external space access on
generation of the NOP cycle that follows reading of the
vector address.
If, however, the CSSTP2 bit is 1, bus mastership is
retained until all transfer is complete, regardless of the
setting of this bit.
0: The bus is released on generation of the NOP cycle by
1: The bus is not released on generation of the NOP
Reserved
This bit is always read as 0. The write value should
always be 0.
Select Bus Release during Burst-Mode-DMAC/DTC
Transfer
This setting applies to DTC transfer when the DTLOCK
bit is 0 and burst-mode DMAC transfer when the DMAC
is in channel-fixed mode, and the activating request was
an external request or was from MTU2. The value
specifies whether the bus mastership is or is not to be
released after each round of transfer in response to a
request from the CPU for access to the external space.
•
0: Release the bus after each round of data transfer.
1: Only release the bus after all data transfer is complete.
Note: In round-robin mode, the bus is only released after
•
0: When the DTLOCK and CSSTP1 bits are 0, the bus is
1: Only release the bus mastership after all data transfer
the DTC.
cycle by the DTC.
released on generation of the NOP cycle after reading
of the vector address. When the DTLOCK bit is 0 and
the CSSTP1 bit is 1, the bus is released after each
round of data transfer.
is complete.
DMAC transfer
DTC transfer
all data transfer is complete, regardless of the
setting of this bit.