DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 15

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.5 Usage Notes ....................................................................................................................... 421
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) ...................................425
11.1 Features.............................................................................................................................. 425
11.2 Input/Output Pins ............................................................................................................... 431
11.3 Register Descriptions ......................................................................................................... 432
10.4.3 Channel Priority.................................................................................................... 402
10.4.4 DMA Transfer Types............................................................................................ 406
10.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 415
10.4.6 Operation Timing.................................................................................................. 419
10.5.1 Notes on Output from DACK Pin......................................................................... 421
10.5.2 DMA Transfer by Peripheral Modules ................................................................. 421
10.5.3 Module Standby Mode Setting ............................................................................. 421
10.5.4 Access to DMAC and DTC Registers through DMAC ........................................ 422
10.5.5 Note on SCI as DMAC Activation Source ........................................................... 422
10.5.6 CHCR Setting ....................................................................................................... 422
10.5.7 Note on Multiple Channel Activation................................................................... 422
10.5.8 Note on Transfer Request Input ............................................................................ 422
10.5.9 Conflict between NMI Interrupt and DMAC Activation ...................................... 422
10.5.10 Number of Cycles per Access to On-Chip RAM by DMAC ................................ 423
10.5.11 Note on DMAC Transfer in Burst Mode when Activation Source is MTU2 ....... 423
10.5.12 Bus Function Extending Register (BSCEHR) ...................................................... 423
11.3.1 Timer Control Register (TCR).............................................................................. 436
11.3.2 Timer Mode Register (TMDR) ............................................................................. 440
11.3.3 Timer I/O Control Register (TIOR) ...................................................................... 443
11.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) .................................... 462
11.3.5 Timer Interrupt Enable Register (TIER) ............................................................... 463
11.3.6 Timer Status Register (TSR)................................................................................. 468
11.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 476
11.3.8 Timer Input Capture Control Register (TICCR) ................................................... 477
11.3.9 Timer Synchronous Clear Register (TSYCR)....................................................... 479
11.3.10 Timer A/D Converter Start Request Control Register (TADCR) ......................... 481
11.3.11 Timer A/D Converter Start Request Cycle Set Registers
11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
11.3.13 Timer Counter (TCNT)......................................................................................... 485
11.3.14 Timer General Register (TGR) ............................................................................. 485
11.3.15 Timer Start Register (TSTR) ................................................................................ 486
11.3.16 Timer Synchronous Register (TSYR)................................................................... 488
(TADCORA_4 and TADCORB_4)...................................................................... 484
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 484
Rev. 3.00 May 17, 2007 Page xv of lviii