DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 459

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

(3)
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.
The DMA receives ten transfer request signals in total: five compare match and input capture
interrupts from multi-function timer pulse unit 2 (MTU2), receive data full interrupts (RXI) and
transmit data empty interrupts (TXI) from two serial communication interface (SCI) channels, and
the A/D conversion end interrupt (ADI) from the A/D converter.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
The transfer request source does not need to be the data transfer source or destination. However,
when the transmit data empty transfer request (TXI) from the SCI is specified as the transfer
request source, the transfer destination must be the transmit data register (TDR) in the respective
SCI channel. Similarly, when the receive data full transfer request (RXI) in the SCI is specified as
the request source, the transfer source must be the receive data register (RDR) in the respective
SCI channel. When the A/D conversion end transfer request (ADI) is specified as the transfer
request source, the transfer source must be the respective register in the A/D converter.
Table 10.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
Notes: MTU2: Multi-function timer pulse unit 2
RS3 RS2 RS1 RS0
0
1
On-Chip Peripheral Module Request Mode
1
0
1
SCI_0 and SCI_1: Serial communication interface channels 0 and 1
ADDR4 to ADDR7: A/D data register in A/D converter channel 1
SCTDR_0 and SCTDR_1: Transmit data registers in SCI_0 and SCI_1
SCRDR_0 and SCRDR_1: Receive data registers in SCI_0 and SCI_1
*
An external memory, a memory-mapped external device, an on-chip memory, or an on-
chip peripheral module (except DMAC, DTC, BSC, and UBC)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Transfer
Request Source
MTU2
MTU2
MTU2
MTU2
MTU2
A/D_1
SCI_0 transmitter TXI_0
SCI_0 receiver
SCI_1 transmitter TXI_1
SCI_1 receiver
Transfer
Request Signal
TGIA_0
TGIA_1
TGIA_2
TGIA_3
TGIA_4
ADI1
RXI_0
RXI_1
Section 10 Direct Memory Access Controller (DMAC)
Source
Any*
Any*
Any*
Any*
Any*
ADDR4 to
ADDR7
Any*
SCRDR_0
Any*
SCRDR_1
Rev. 3.00 May 17, 2007 Page 401 of 1582
Destination Bus Mode
Any*
Any*
Any*
Any*
Any*
Any*
SCTDR_0
Any*
SCTDR_1
Any*
Burst or cycle steal
Burst or cycle steal
Burst or cycle steal
Burst or cycle steal
Burst or cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
REJ09B0181-0300