DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 254

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Data Transfer Controller (DTC)
Transfer source data area
Transfer destination data area
SAR
DAR
Transfer
Figure 8.6 Memory Map in Normal Transfer Mode
8.5.4
Repeat Transfer Mode
In repeat transfer mode, data are transferred in one byte, one word, or one longword units in
response to a single activation request. By the DTS bit in MRB, either the source or destination
can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified
number of transfers ends, the transfer counter and address register specified as the repeat area is
restored to the initial state, and transfer is repeated. The other address register is then incremented,
decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the
value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not
reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0.
Table 8.7 lists the register function in repeat transfer mode. Figure 8.7 shows the memory map in
repeat transfer mode.
Rev. 3.00 May 17, 2007 Page 196 of 1582
REJ09B0181-0300