DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 633

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15. Suppressing MTU2–MTU2S Synchronous Counter Clearing
Figure 11.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC
TGRA_3
TGRB_3
In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing
caused by the MTU2.
Synchronous counter clearing is suppressed only within the interval shown in figure 11.62.
When using this function, the MTU2S should be set to complementary PWM mode.
For details of synchronous clearing caused by the MTU2, refer to the description about
MTU2S counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous
counter clearing) in section 11.4.10, MTU2–MTU2S Synchronous Operation.
H'0000
TCDR
TDDR
Tb interval
immediately
after counter
operation starts
MTU2-MTU2S synchronous counter
clearing is suppressed.
Tb interval
at the crest
Bit in TWCR
at the trough
Tb interval
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2-MTU2S synchronous counter
Rev. 3.00 May 17, 2007 Page 575 of 1582
clearing is suppressed.
Tb interval
at the crest
REJ09B0181-0300
at the trough
Tb interval

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