DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 887

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.4
16.4.1
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses. The SCIF has a 16-byte FIFO buffer for both transmit and receive
operations, reducing the overhead of the CPU, and enabling continuous high-speed
communication. Moreover, it has RTS and CTS signals as modem control signals. The
transmission format is selected in the serial mode register (SCSMR) as shown in table 16.13. The
SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control
register (SCSCR) as shown in table 16.14.
(1)
• Data length is selectable: 7 or 8 bits.
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding
• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full,
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the SCIF clock source.
(2)
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCIF clock source.
selections constitutes the communication format and character length.
overrun errors, receive data ready, and breaks.
 When an internal clock is selected, the SCIF operates using the on-chip baud rate
 When an external clock is selected, the external clock input must have a frequency 16 times
 When an internal clock is selected, the SCIF operates using the on-chip baud rate
 When an external clock is selected, the SCIF operates on the input serial clock. The on-
Asynchronous Mode
Clock Synchronous Mode
generator.
the bit rate. (The on-chip baud rate generator is not used.)
generator, and outputs a serial clock signal to external devices.
chip baud rate generator is not used.
Operation
Overview
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 May 17, 2007 Page 829 of 1582
REJ09B0181-0300