DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 40

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 17.13 Example of Transmission Operation
Figure 17.14 Flowchart Example of Transmission Operation
Figure 17.15 Example of Reception Operation
Figure 17.16 Flowchart Example of Data Reception
Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception
Section 18 I
Figure 18.1 Block Diagram of I
Figure 18.2 External Circuit Connections of I/O Pins ................................................................ 903
Figure 18.3 I
Figure 18.4 I
Figure 18.5 Master Transmit Mode Operation Timing (1)......................................................... 922
Figure 18.6 Master Transmit Mode Operation Timing (2)......................................................... 922
Figure 18.7 Master Receive Mode Operation Timing (1) .......................................................... 924
Figure 18.8 Master Receive Mode Operation Timing (2) .......................................................... 925
Figure 18.9 Slave Transmit Mode Operation Timing (1) ........................................................... 927
Figure 18.10 Slave Transmit Mode Operation Timing (2) ......................................................... 928
Figure 18.11 Slave Receive Mode Operation Timing (1)........................................................... 929
Figure 18.12 Slave Receive Mode Operation Timing (2)........................................................... 930
Figure 18.13 Clock Synchronous Serial Transfer Format .......................................................... 930
Figure 18.14 Transmit Mode Operation Timing......................................................................... 931
Figure 18.15 Receive Mode Operation Timing .......................................................................... 933
Figure 18.16 Operation Timing For Receiving One Byte .......................................................... 933
Figure 18.17 Block Diagram of Noise Filter .............................................................................. 934
Figure 18.18 Sample Flowchart for Master Transmit Mode ...................................................... 935
Figure 18.19 Sample Flowchart for Master Receive Mode ........................................................ 936
Figure 18.20 Sample Flowchart for Slave Transmit Mode......................................................... 937
Figure 18.21 Sample Flowchart for Slave Receive Mode .......................................................... 938
Figure 18.22 The Timing of the Bit Synchronous Circuit .......................................................... 941
Section 19 A/D Converter (ADC)
Figure 19.1 Block Diagram of A/D Converter (for One Module) .............................................. 946
Figure 19.2 A/D Conversion Timing.......................................................................................... 964
Figure 19.3 External Trigger Input Timing ................................................................................ 966
Figure 19.4 Example of 2-Channel Scanning ............................................................................. 967
Figure 19.5 Definitions of A/D Conversion Accuracy ............................................................... 970
Rev. 3.00 May 17, 2007 Page xl of Iviii
2
2
2
C Bus Interface 2 (I
(Clock Synchronous Communication Mode) ........................................................ 893
(Clock Synchronous Communication Mode) ........................................................ 894
(Clock Synchronous Communication Mode) ........................................................ 895
(Clock Synchronous Communication Mode) ........................................................ 896
(Clock Synchronous Communication Mode) ........................................................ 897
C Bus Formats ...................................................................................................... 920
C Bus Timing........................................................................................................ 920
2
C Bus Interface 2..................................................................... 902
2
C2)