DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 201

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.3.5
BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data
specified by BDRA.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
Initial value:
Initial value:
Bit
31 to 0 BDMA31 to
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16
BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9
Bit Name
BDMA 0
R/W
R/W
Break Data Mask Register A (BDMRA) (Only in F-ZTAT Version)
31
15
0
0
bits 15 to 8 and 7 to 0 in BDMRA as the break mask data in BDRA.
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
Break Data Mask A
Specifies bits masked in the break data of channel A
specified by BDRA (BDA31 to BDA0).
0: Break data BDAn of channel A is included in the
1: Break data BDAn of channel A is masked and is not
Note: n = 31 to 0
R/W
R/W
25
0
9
0
break condition
included in the break condition
BDMA8
R/W
R/W
24
0
8
0
BDMA7
R/W
R/W
23
0
7
0
BDMA6
R/W
R/W
Rev. 3.00 May 17, 2007 Page 143 of 1582
22
0
6
0
Section 7 User Break Controller (UBC)
BDMA5
R/W
R/W
21
0
5
0
BDMA4
R/W
R/W
20
0
4
0
BDMA3
R/W
R/W
19
0
3
0
REJ09B0181-0300
BDMA2
R/W
R/W
18
0
2
0
BDMA1
R/W
R/W
17
0
1
0
BDMA0
R/W
R/W
16
0
0
0