DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1036

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 20 Compare Match Timer (CMT)
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 3.00 May 17, 2007 Page 978 of 1582
REJ09B0181-0300
Bit
15 to 8
7
6
5 to 2
1, 0
2. If the flag is set by another compare match before writing 0 to the bit after reading it as
Bit Name

CMF
CMIE

CKS[1:0]
1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again
and write 0 to it.
00
Initial
value
All 0
0
0
All 0
R/W
R
R/(W)*
R/W
R
R/W
1
Clock Select 1 and 0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing conditions]
•
•
[Setting condition]
1: CMCNT and CMCOR values match
Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF=1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Select the clock to be input to CMCNT from four internal
clocks obtained by dividing the peripheral operating
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
When 0 is written to this bit after reading CMF=1*
When CMT registers are accessed when the value
of the DISEL bit of MRB in the DTC is 0 after
activating the DTC by CMI interrupts.
2