DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 31

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 9.45 Burst MPX Space Access Timing
Figure 9.46 Burst MPX Space Access Timing (Burst Read, No Wait or Software Wait 1) ...... 354
Figure 9.47 Burst MPX Space Access Timing (Burst Write, No Wait) ..................................... 355
Figure 9.48 Burst ROM (Clock Synchronous) Access Timing
Figure 9.49 Bus Arbitration when DTC and DMAC Compete during External Space Access
Figure 9.50 Bus Arbitration when DTC or DMAC Activation Request Occurs during
Figure 9.51 Bus Arbitration Timing ........................................................................................... 375
Figure 9.52 Timing of Write Access to On-Chip Peripheral I/O Registers
Figure 9.53 Timing of Read Access to On-Chip Peripheral I/O Registers
Figure 9.54 Timing of Write Access to Word Data in External Memory
Figure 9.55 Timing of Read Access with Condition Iφ:Bφ = 4:1
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 Block Diagram of DMAC ....................................................................................... 384
Figure 10.2 DMA Transfer Flowchart ........................................................................................ 398
Figure 10.3 Round-Robin Mode................................................................................................. 403
Figure 10.4 Changes in Channel Priority in Round-Robin Mode............................................... 404
Figure 10.5 Example of Activation Priority Operation of DMAC
Figure 10.6 Data Flow of Dual Address Mode........................................................................... 407
Figure 10.7 Example of DMA Transfer Timing in Dual Mode
Figure 10.8 Data Flow in Single Address Mode......................................................................... 409
Figure 10.9 Example of DMA Transfer Timing in Single Address Mode.................................. 410
Figure 10.10 DMA Transfer Example in Cycle-Steal Normal Mode
Figure 10.11 Example of DMA Transfer in Cycle Steal Intermittent Mode
Figure 10.12 DMA Transfer Example in Burst Mode
Figure 10.13 Bus State when Multiple Channels are Operating ................................................. 414
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 415
(Single Write, Software Wait 1, Hardware Wait 1)................................................. 353
(Burst Length = 8, Access Wait for the 1st time = 2,
Access Wait for 2nd Time after = 1) ....................................................................... 356
from CPU ................................................................................................................ 371
External Space Access from CPU ........................................................................... 373
When Iφ:Bφ:Pφ = 4:2:2 ........................................................................................... 379
When Iφ:Bφ:Pφ = 4:2:1 ........................................................................................... 379
When Iφ:Bφ = 2:1 and External Bus Width is 8 Bits............................................... 381
and External Bus Width ≥ Data Width .................................................................... 382
(Priority Fixed Mode (CH0 > CH1 > CH2 > CH3))................................................ 405
(Source: Ordinary Memory, Destination: Ordinary Memory)................................. 408
(Dual Address, DREQ Low Level Detection) ....................................................... 411
(Dual Address, DREQ Low Level Detection) ....................................................... 411
(Dual Address, DREQ Low Level Detection) ....................................................... 412
Rev. 3.00 May 17, 2007 Page xxxi of Iviii