DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 391

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
After self-refreshing has been specified, the SDRAM stays in the self-refresh state even after
this LSI enters the standby state. The self-refresh state continues after recovery from the
standby state by interrupt. However, the CKE and other pins must be driven in the standby
state by setting the HIZCNT bit in the CMNCR register to 1.
The self-refresh state is not cleared by a manual reset.
In case of a power-on reset, the bus state controller’s registers are initialized, and therefore the
self-refresh state is cleared.
RASL, RASU
CASL, CASU
A12/A11*
D31 to D0
A25 to A0
DACKn*
Notes: 1.
DQMxx
RDWR
CKE
CSn
CK
BS
2.
1
2
Address pin to be connected to pin A10 of SDRAM.
The waveform for DACKn is when active low is specified.
Tp
Tpw
Figure 9.29 Self-Refresh Timing
Trr
Hi-z
Trc
Rev. 3.00 May 17, 2007 Page 333 of 1582
Trc
Section 9 Bus State Controller (BSC)
Trc
Trc
REJ09B0181-0300
Trc

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