DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1009

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
10
9
8
7, 6
Bit Name

CONADF
STC
CKSL[1:0] 00
Initial
Value
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
ADF Control
Controls setting of the ADF bit in 2-channel scan
mode. The setting of this bit is valid only when
triggering of A/D conversion is enabled (TRGE = 1) in
2-channel scan mode. The setting of this bit is ignored
in single mode, 4-channel scan mode, or 8-channel
scan mode.
0: The ADF bit is set when A/D conversion started by
1: The ADF bit is set when A/D conversion started by
When changing the operating mode, first clear the
ADST bit to 0.
State Control
Sets the A/D conversion time in combination with the
CKSL1 and CKSL0 bits.
0: 50 states
1: 64 states
When changing the A/D conversion time, first clear the
ADST bit to 0.
Clock Select 1 and 0
Select the A/D conversion time.
00: Pφ/4
01: Pφ/3
10: Pφ/2
11: Pφ
When changing the A/D conversion time, first clear the
ADST bit to 0.
CKSL[1:0] = B'11 can be set while Pφ ≤ 25 [MHz].
the group 0 trigger or group 1 trigger has finished.
the group 0 trigger and A/D conversion started by
the group 1 trigger have both finished. Note that the
triggering order has no affect.
Rev. 3.00 May 17, 2007 Page 951 of 1582
Section 19 A/D Converter (ADC)
REJ09B0181-0300