DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 824

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 15 Serial Communication Interface (SCI)
15.4.3
In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver are independent, so full-duplex communication is possible while
sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that
data can be read or written during transmission or reception, enabling continuous data transfer.
Figure 15.8 shows the general format in clock synchronous serial communication.
Rev. 3.00 May 17, 2007 Page 766 of 1582
REJ09B0181-0300
Figure 15.7 shows an example of the operation for reception.
Serial
data
RDRF
FER
Clock Synchronous Mode
Synchronization
clock
Serial data
Note: * High level except in continuous transfer
1
Figure 15.8 Data Format in Clock Synchronous Communication
Start
bit
0
Don't care
Figure 15.7 Example of SCI Receive Operation
D0
*
D1
One frame
(8-Bit Data, Parity, One Stop Bit)
LSB
Bit 0
Data
D7
One unit of transfer data (character or frame)
Bit 1
RXI interrupt
request
Parity
bit
0/1
Bit 2
Stop
bit
1
Start
bit
Bit 3
0
Data read and RDRF flag
cleared to 0 by RXI
interrupt handler
D0
Bit 4
D1
Data
Bit 5
D7
Bit 6
Parity
bit
0/1
Stop
bit
MSB
ERI interrupt request
generated by framing
error
Bit 7
1
Don't care
*
0/1