DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1610

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev. 3.00 May 17, 2007 Page 1552 of 1582
REJ09B0181-0300
Item
Figure 11.88 Example of External
Pulse Width Measurement
(Measuring High Pulse Width)
11.7.22 Simultaneous Capture of
TCNT_1 and TCNT_2 in Cascade
Connection
Table 13.5 Interrupt Sources and
Conditions
13.6 Usage Note
Figure 14.3 Operation in
Watchdog Timer Mode
(When WTCNT Count Clock is
Specified to Pφ/32 by CKS2 to
CKS0)
Page Revision (See Manual for Details)
601
638
710
711
721
Amended
Added
….In this case, the values of TCNT_1 = H'FFF1 and
TCNT_2 = H'0000 should be transferred to TGRA_1
and TGRA_2 or to TGRB_1 and TGRB_2, but the
values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are
erroneously transferred.
The MTU2 has a new function that allows simultaneous
capture of TCNT_1 and TCNT_2 with a single input-
capture input as the trigger. This function allows reading
of the 32-bit counter such that TCNT_1 and TCNT_2
are captured at the same time. For details, see section,
11.3.8, Timer Input Capture Control Register (TICCR).
Amended
Added
Amended
Name
OEI3
OEI2
TCNT5_U
Internal reset signal
(power-on reset selected)
Internal reset signal
(manual reset selected)
TIC5U
MPφ
0000
Interrupt Source
Output enable interrupt 3
Output enable interrupt 2
0001 0002 0003 0004 0005 0006 0007
3 Pφ + one cycle of count clock
18 Pφ clock
0007
0008 0009
000A 000B