DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 951

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

(2)
Figure 17.13 shows an example of transmission operation, and figure 17.14 shows a flowchart
example of data transmission. When transmitting data in clock synchronous communication mode,
the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is
input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0 before transmission.
User operation
LSI operation
Data Transmission
SSCK
TDRE
TEND
SSO
Data written
to SSTDR
TXI interrupt
generated
Figure 17.13 Example of Transmission Operation
(Clock Synchronous Communication Mode)
Bit 0
Data written
to SSTDR
Bit 1
1 frame
Section 17 Synchronous Serial Communication Unit (SSU)
Bit 7
TXI interrupt
generated
Rev. 3.00 May 17, 2007 Page 893 of 1582
Bit 0
Bit 1
1 frame
REJ09B0181-0300
TEI interrupt
generated
Bit 7