DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 397

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9.5.8
The SRAM interface with byte selection is a memory interface which outputs a byte-selection pin
(WRxx) in a read/write bus cycle. This interface has 16-bit data pins and accesses SRAMs having
upper and lower byte-selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM
interface with byte selection is the same as that for the normal space interface. While in read
access of the SRAM interface with byte selection, the byte-selection signal is output from the
WRxx pin, which is different from that for the normal space interface. The basic access timing is
shown in figure 9.32. In write access, data is written to memory according to the timing of the
byte-selection pin (WRxx). For details, refer to the Data Sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WRxx pin and RDWR pin timings change. Figure 9.33
shows the basic access timing. In write access, data is written to memory according to the timing
of the write enable pin (RDWR). The data hold timing from RDWR negation to data write must be
acquired by setting the HW1 and HW0 bits in the CSnWCR register. Figure 9.34 shows the access
timing when a software wait is specified.
SRAM Interface with Byte Selection
D31 to D0
Access Wait for the 1st time = 2, Access Wait for 2nd Time and after = 1)
Address
RDWR
DACK
WAIT
RD
CK
CS
BS
(Bus Width = 32 Bits, 16 byte Transfer (Number of Burst = 4),
Figure 9.31 Burst ROM (Clock Asynchronous) Access
T1
Tw
Tw
TB2
Twb
TB2
Twb
Rev. 3.00 May 17, 2007 Page 339 of 1582
Section 9 Bus State Controller (BSC)
TB2
Twb
T2
REJ09B0181-0300