DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 224

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
Break Condition Specified for L Bus Data Access Cycle:
(Example 2-1)
• Register specifications
Rev. 3.00 May 17, 2007 Page 166 of 1582
REJ09B0181-0300
Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed
or before an instruction with addresses H'00008010 to H'00008016 are executed.
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BDRA = H'12345678,
BDMRA = H'FFFFFFFF, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A,
BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Data:
Bus cycle: L bus/data access/read (operand size is not included in the condition)
<Channel B>
Address:
Data:
Bus cycle: L bus/data access/write/word
On channel A, a user break occurs with longword read from address H'00123454, word read
from address H'00123456, or byte read from address H'00123456. On channel B, a user break
occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.
included in the condition)
H'00008010, Address mask: H'00000006
H'00000000, Data mask: H'00000000
included in the condition)
H'00123456, Address mask: H'00000000
H'12345678, Data mask: H'FFFFFFFF
H'000ABCDE, Address mask: H'000000FF
H'0000A512, Data mask: H'00000000