DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 964

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
Rev. 3.00 May 17, 2007 Page 906 of 1582
REJ09B0181-0300
Bit
6
5
4
3 to 0
Bit Name
RCVD
MST
TRS
CKS[3:0]
2
C Bus Interface 2 (I
Initial
Value
0
0
0
0000
2
C2)
R/W
R/W
R/W
R/W
R/W
Description
Reception Disable
When TRS = 0, this bit enables or disables continuous
reception without reading of ICDRR. In master receive
mode, when ICDRR cannot be read before the rising
edge of the 8th clock of SCL, set RCVD to 1 so that
data is received in byte units.
0: Enables continuous reception
1: Disables continuous reception
Master/Slave Select
Transmit/Receive Select
In master mode with the I
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
When seven bits after the start condition is issued in
slave receive mode match the slave address set to
SAR and the 8th bit is set to 1, TRS is automatically
set to 1. If an overrun error occurs in master receive
mode with the clock synchronous serial format, MST is
cleared and the mode changes to slave receive mode.
Operating modes are described below according to
MST and TRS combination. When clock synchronous
serial format is selected and MST = 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select 3 to 0
These bits should be set according to the necessary
transfer rate (table 18.3) in master mode. In slave
mode, these bits should be used to specify the data
setup time in transmission mode. The setup time is set
to 10 tpcyc when CKS3 = 0 or 20 tpcyc when CKS3 =
1 (tpcyc is one Pφ cycle).
2
C bus format, when